Exemplary embodiments of the present invention relate to a semiconductor memory device and a manufacturing method thereof, and more particularly, to a semiconductor memory device using a variable resistance element, and a manufacturing method thereof.
In general, a semiconductor memory device includes a large number of memory cells. A representative semiconductor memory device is a dynamic random access memory (DRAM). A typical unit memory cell of a DRAM includes one switch and one capacitor. A DRAM has a high integration density and a fast operating speed. However, because a DRAM implements “0” and “1” according to a change in the quantity of electric charge, a DRAM is a volatile memory device, which loses stored data after power is interrupted. That is, a DRAM has difficulty retaining data. To address this concern, research into new memory technology has been conducted to implement a binary state corresponding to “0” and “1” of a DRAM by using other characteristics, instead of the quantity of electric charge.
Examples of nonvolatile memory devices which have been recently researched include a magnetic random access memory (MRAM) configured with a magneto-resistance element using a magneto-resistance effect, a ferroelectric random access memory (FRAM) configured with a ferroelectric element using a polarization characteristic of a ferroelectric material, and a phase-change random access memory (PRAM) configured with a phase-change element using a phase-change material. In addition, research and development has been rapidly conducted on a resistance switching random access memory (ReRAM), which uses an element that exists as an insulator in an inherent state and changes to a metal or semiconductor state when an external voltage is applied. In the case of memory devices based on such a variable resistance element, it is necessary to supply a relatively large amount of electric current in order to write and read data. Further, in order to configure a highly integrated memory, it is necessary to minimize the influence of external resistance, such as resistance of signal lines through which signals are inputted and outputted.
Meanwhile, signal lines in a cell array of a semiconductor memory device are configured to connect elements, such as source lines, transistors, variable resistance elements (storage nodes), and bit lines, through several contact plugs. However, in the case in which electrical paths are configured through several contact plugs, there is a limitation on reducing a total resistance of signal lines due to reduction in a contact area caused by a down-scaling of the memory device. Down-scaling a memory device may increase a resistance of its contact plugs and an interfacial resistance, which is generated in a contact region between the contact plugs and the elements. In the case of a memory device using a variable resistance element, it is particularly desirable to reduce an electrical resistance of signal lines, such as source lines and bit lines. In general, an electrical resistance of signal lines may be reduced by using a material having a high electrical conductivity or increasing the height and width of metal interconnections. However, such methods may limit the degree of integration of the memory device. Therefore, there is a demand for a new manufacturing process that produces a memory device, having a variable resistance element, which may have a reduced external resistance while an external signal is inputted and outputted, so that a high integration of the memory device may be achieved.